The present invention relates to semiconductor memory devices, and in particular to random access memory (RAM) devices having a configurable depth and width.
Conventional RAM devices include memory cells that are arranged in columns and rows. When writing a data bit into a particular memory cell, the data bit is provided on a bit line for an entire column of memory cells. A particular memory cell along the column is then selected for storing the information bit by providing a row selection signal on a particular write word line. The number of selectable memory cells or elements in the RAM device is known as the depth of the device. The depth of the RAM device is a function of the number of address bits received by the RAM device. The width of the RAM device is the number of data bits that can be stored in the RAM device per address location. Conventionally, the depth and width of a RAM device is fixed.
FIG. 1 shows a simplified view of a conventional RAM device 10. RAM device 10 is shown as having a six bit address port 12 and a two bit wide data word input port 14 and output port 15. RAM device 10 is also shown as having write and read select ports 16 and 18, respectively.
Because conventional RAM device 10 has a six bit address port 12, RAM device 10 has a depth of 64 elements (26=64). Because RAM device 10 has a two bit data word input and output ports 14 and 15, RAM device 10 has a width of 2. Thus, RAM device 10 has a size of 64xc3x972, which is fixed.
Blocks of RAM devices are sometimes used in programmable logic devices as building blocks to generate larger RAM devices. When a user desires a RAM device having a greater depth and/or width, the user programs the programmable logic device to combine multiple RAM devices. The combination of multiple RAM devices, where each individual device has a fixed depth and width, results in a greater depth and/or width.
A user conventionally increases the width of a RAM device by combining multiple RAM devices as shown in FIG. 2. FIG. 2 shows a simplified view of two 64xc3x972 RAM devices 10 and 30 combined to form a circuit 28 with an increased width of 64xc3x974. Only the address ports 12, 32 and the data output ports 15, 35 are shown on RAM devices 10, 30, respectively, for the sake of simplicity. As shown in FIG. 2, the address ports of the two RAM devices 10 and 30 are combined in pairs. The total number of address bits received by the address ports 15 and 35 of the RAM devices 10 and 30 remains the same and, thus, the total depth remains 64. As shown in FIG. 2, the combination of RAM devices 10 and 30 results in four data output ports 15 and 35. Thus, by combining RAM devices 10 and 30 as shown in FIG. 2, the total width of the data bits that may be stored is increased by 2.
If a user desires a RAM device with an increased number of addressable elements, the user conventionally combines multiple RAM devices as shown in FIGS. 3A and 3B. FIGS. 3A and 3B show a simplified view of two 64xc3x972 RAM devices 10 and 30 combined to form circuits 38 and 39 with an increased depth of 128xc3x972 for write operations and read operations, respectively. The respective address ports 12 and 32 of RAM devices 10 and 30 are combined as in FIG. 2. As shown in FIG. 3A, for write operations, circuit 38 increases the depth from 64, i.e., 6 address ports, to 128, i.e., 7 address ports, with logic gates such as AND gate 40 and AND gate 42 coupled to enable control ports 11 and 31, respectively. As shown in FIG. 3A, AND gate 42 has a inverter at the write address 6 input terminal, i.e., the seventh address port. The input terminals of logic gates 40 and 42 are coupled together. As shown in FIG. 3B, for read operations, circuit 39 has the data output ports 15, 35 coupled to input terminals of a multiplexor (MUX) 44, shown as having two multiplexors, which selects the desired output ports. The read address 6 input terminal, i.e., the seventh address port, is coupled to the select terminal of MUX 44, which selects the appropriate data output ports based on the select signal. Thus, circuits 38 and 39 have effective RAM device sizes of 128xc3x972. The depth of circuits 38 and 39 may be further increased by combining additional RAM devices in a similar manner. Unfortunately, each increase in depth requires the use of additional logic gates. The use of logic gates, however, slows the speed of the RAM device and requires additional power.
To avoid the use of many logic gates, large RAM devices may be manufactured. However, large RAM devices are expensive and utilizes a large amount of space on the chip. If the user desires only a small amount of RAM, the cost and space of the large RAM will be wasted.
A RAM device, such as the type embedded in a programmable logic device, is configurable to alter the depth of the addressable elements and the width of the number of data bits stored in the RAM device per address. The RAM device includes a number of address ports for receiving the read and/or write address signals. However, for a shallow configuration of the RAM device, the RAM device receives fewer address signals then there are address ports. Consequently, in shallow configurations, a number of address ports will not be used. Likewise, the RAM device includes a number of input and output data ports, but the width of the RAM device may be configured such that the number of data bits actually stored in the RAM device is less than the number of data ports. Thus, in narrow configurations, a number of the input and output data ports will not be utilized.
The depth and the width of the RAM device are configured together so that the depth is increased when the width is decreased and vice versa. This permits the user to configure a number of RAM devices to the desired depth. The RAM devices may then be combined easily to increase the width. Consequently, the user can configure the RAM devices to be deep, wide, or both without the use of logic gates that would reduce the speed of the device. Further, because the RAM device is configurable, the user can use the amount of RAM desired and does not unnecessarily waste the RAM.